[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #30 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #28)
> (In reply to Luke Kenneth Casson Leighton from comment #27)
> oder.py;h=0e0f1f22e5f9d1a92d8362f49cdb6b62c42b0ec4;hb=HEAD
> > 
> > that was quick and pretty ridiculously easy, wasn't it? :)
> 
> yup
> 
> > heck no, the whole point is to be able to do wget on the wiki version
> > (rather than have two out-of-date copies)
> 
> It doesn't look like I have write access to the wiki git,

you do now.  git clone gitolite3 at git.libre-riscv.org:922/libreriscv.git
i think.  check HDL_workflow.

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