[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ehhm.. ehmehmehm.... i am getting confused, sorry, i was looking for certain
patterns, spotted half of what i expected to be there and thought it was the
whole lot.

load2 is... oh wait! it's... yes they are both strided, yes i see the address
computation is in the loop.

ok yes got it, yes load2 is how it's done, with the Dependency Matrices
protecting both the memory reads (from writes) *and* protecting the register
reads and writes... in full sequence.

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