[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #17)
> (In reply to Jacob Lifshay from comment #14)
> 
> > // what I think SimpleV should be defined to do
> 
> (... it's not)
> 
> > void load1(int address_reg, int dest_reg, int N)
> > {
> >     int address = regs[address_reg];
> >     for(int i = 0; i < N; i++)
> >         regs[dest_reg + i] = *(int *)(address + sizeof(int) * i);
> > }
> > 
> > // what SimpleV is currently defined to do
> 
> (... it's not)
> 
> > void load2(int address_reg, int dest_reg, int N)
> > {
> >     for(int i = 0; i < N; i++)
> >         regs[dest_reg + i] = *(int *)(regs[address_reg] + sizeof(int) * i);
> > }
> 
> it has support for both.  the first is called 'indirect mode', the
> second is 'stride mode'.

umm...

strided mode is conventionally where the addresses loaded follow the sequence
base + i * increment where increment can be much bigger than sizeof(int)

indirect mode is conventionally where the addresses are taken from successive
vector elements so each address can be independently specified.

what load2 is is where the address register is a scalar that doesn't change
(address_reg is never reassigned), but regs[address_reg] is assigned to halfway
through, changing the address used for subsequent loads. This is what's
specified for compact loads (for lack of a better term).

-- 
You are receiving this mail because:
You are on the CC list for the bug.