[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #9)
> (In reply to Luke Kenneth Casson Leighton from comment #6)
> > therefore, lmw can quite literally be replaced with a SimpleV
> > "SVPrefix" instruction.  SVP{VL=32}.LD r1, r2#D.
> 
> One thing to consider: lmw and similar is probably defined to read the
> address register before writing to any registers, whereas SimpleV may not be
> defined that way (but probably should be), this matters when the load
> overwrites the address register part way through.

that's handled by the LD Function Unit.  Reservations are put on the
registers (and on the memory address... *when calculated*).

you need to read mitch alsup's book chapters to fully understand the process.

and yes, the Dependency Matrix will notice that there is a write hazard
on the address being overwritten, and will correctly "hold up" the
instruction that depends on the register.

from what you're saying, michael, this is "too complicated" for POWER ISA
to cope with, so they declare it "invalid"?  if so this does not surprise me
at all because you absolutely cannot have an ISA that specifically depends
on an OoO execution model.

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