[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #11 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Jacob Lifshay from comment #9)
> 
> One thing to consider: lmw and similar is probably defined to read the
> address register before writing to any registers, whereas SimpleV may not be
> defined that way (but probably should be), this matters when the load
> overwrites the address register part way through.

The POWER ISA declares a LMW like that (or a LMW including register 0) to be
invalid because of this. Glad you brought it up though

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