[libre-riscv-dev] [Bug 21] LPDDR3/LPDDR4 needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Feb 24 14:24:54 GMT 2020


--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #6)

> Nit: both SDR SDRAM and DDR SDRAM are synchronous (that's the S in SDRAM).

ah appreciated the correction.

> On a more constructive note, would it be feasible to do DDR1 or DDR2
> ourselves?

not in the timescales we have.


You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list