[libre-riscv-dev] [Bug 21] LPDDR3/LPDDR4 needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=21

--- Comment #7 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #6)

> Nit: both SDR SDRAM and DDR SDRAM are synchronous (that's the S in SDRAM).

ah appreciated the correction.

> On a more constructive note, would it be feasible to do DDR1 or DDR2
> ourselves?

not in the timescales we have.

l.

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