[libre-riscv-dev] [Bug 21] LPDDR3/LPDDR4 needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Feb 24 14:13:28 GMT 2020


Michael Nolan <mtnolan2640 at gmail.com> changed:

           What    |Removed                     |Added
                 CC|                            |mtnolan2640 at gmail.com

--- Comment #6 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> (In reply to Jacob Lifshay from comment #4)
> > Oh well, my ideas for the DLL might be useful for something else :)
> when we have large funding, yes.
> SDRAM is asynchronous and is basically XT bus aka AT Bus aka 8080 MCU bus
> aka FlexBus aka IDE Bus aka PCMCIA bus aka CompactFlash Bus aka ONFI NAND
> Bus.
> all of these are literally the same fundamental async bus all from the same
> era (IBM / Intel) using WEN REN CS# wires etc etc etc etc. it just got
> faster and hit a practical limit of around 133 mhz.
> DDR2 went synchronous clock driven and that's when it got complicated.

Nit: both SDR SDRAM and DDR SDRAM are synchronous (that's the S in SDRAM).

On a more constructive note, would it be feasible to do DDR1 or DDR2 ourselves?
IIRC the interface is a bit simpler:
 - Slower speed
 - No differential IOs (not countitng the clock) on DDR1 at least
 - Data signals are terminated with resistors to VCC not VCC/2

I think we'd still need a DLL or PLL, though Jacob's suggestion of using a PLL
at 2x the transfer frequency would be easier here than for DDR3/4.

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