[libre-riscv-dev] [Bug 21] LPDDR3/LPDDR4 needed

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Feb 24 08:49:27 GMT 2020


--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)

> Oh well, my ideas for the DLL might be useful for something else :)

when we have large funding, yes.

SDRAM is asynchronous and is basically XT bus aka AT Bus aka 8080 MCU bus aka
FlexBus aka IDE Bus aka PCMCIA bus aka CompactFlash Bus aka ONFI NAND Bus.

all of these are literally the same fundamental async bus all from the same era
(IBM / Intel) using WEN REN CS# wires etc etc etc etc. it just got faster and
hit a practical limit of around 133 mhz.

DDR2 went synchronous clock driven and that's when it got complicated.

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