[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #62 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #61)
> Hello Luke,
> 
> Could you produce a log file with this change in your
> coriolis2/settings.py :

http://ftp.libre-riscv.org/soclayout.tgz

> Cfg.getParamBool( 'misc.logMode' ).setBool( True )
> 
> This will suppress the "counting" effect in the router's output and
> make it easier to compare.
> 
> In theory, Coriolis2 is deterministic, but is assumes that we have
> exactly the same executing context. For example, that we have the
> same Yosys. Maybe we can work from the generated blif file.

ok that's in the above .tgz file

> I would also need your users-lkcl.mk.

# Where lkcl gets his tools installeds.

 #export CORIOLIS_TOP  =
$(HOME)/coriolis-2.x/$(BUILD_VARIANT)$(LIB_SUFFIX_)/$(BUILD_TYPE_DIR)/install
 #export ALLIANCE_TOP  =
$(HOME)/alliance/$(BUILD_VARIANT)$(LIB_SUFFIX_)/install
 export CHECK_TOOLKIT = $(HOME)/alliance-check-toolkit
 export YOSYS_TOP     = /usr


> I did go through your log, but did not see obvious problems.
> I have a suspicion but I would need to confirm it with the log.
> 
> My recommandation would be to have one directory per block.

ok. that sounds like a good idea to me anyway.  mind racing ahead
somewhat, we probably should be creating a way to auto-generate
the entire structure based on information in the actual source
code.

are there examples to start from?

> For the block descriptions, we have a constraint, originally
> derived from the fact that we where using VHDL as our main language:
> * One signal <-> one external connector (if any)
> 
> This allows us to implement efficient hierarchical net walkthrough.

ok.  would like to see that in action.

> The second step in experiment would be to build a custom regular
> block. That is procedural netlist building and matrix like placement,
> then automatic routing.

ooo :)

> Making an ASIC is still an art...

lots of small things get in the way, any one of which stops any kind of
incremental progress.  this is why we start small.

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