[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #61 from Jean-Paul.Chaput at lip6.fr ---
Hello Luke,

Could you produce a log file with this change in your
coriolis2/settings.py :

Cfg.getParamBool( 'misc.logMode' ).setBool( True )

This will suppress the "counting" effect in the router's output and
make it easier to compare.

In theory, Coriolis2 is deterministic, but is assumes that we have
exactly the same executing context. For example, that we have the
same Yosys. Maybe we can work from the generated blif file.
I would also need your users-lkcl.mk.

I did go through your log, but did not see obvious problems.
I have a suspicion but I would need to confirm it with the log.

My recommandation would be to have one directory per block.

For the block descriptions, we have a constraint, originally
derived from the fact that we where using VHDL as our main language:
* One signal <-> one external connector (if any)

This allows us to implement efficient hierarchical net walkthrough.

The second step in experiment would be to build a custom regular
block. That is procedural netlist building and matrix like placement,
then automatic routing.

Making an ASIC is still an art...

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