[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #51 from Jean-Paul.Chaput at lip6.fr ---

I now did make work test_part_add (Makefile3).
I almost got part_sig_add to work (Makefile2), but lvx fails due to the
fact that some external terminals of the netlist are, in fact, unconnecteds.
That is, in the netlist, you have "carry_in(4)" which is not connected to
any cell. So the router will not generate any physical wire for it, then
the extractor (cougar) will not extract anything for that net, so the
extracted netlist do not have "carry_in(4)" in its interface. Hence the
lvx failure. I know it may not be very practical for designers, but
would it be possible to remove unconnected nets from the interface?
Otherwise we have to edit the vst to remove them (possibly through all
the hierarchy).

Concerning the $$ problem, I don't see it. The generated blif file do
not contain any.

I've also modified the synthesys-yosys.mk so you shouldn't need to patch
it. So you can just make a link of the "mk" directory (ah, maybe not
because of user's profile).

My advice concerning that repository is that you split it, one directory
per test design. I kept running the wrong MakefileX...

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