[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #50 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ah

        + reorder$20 [.model]
        + reorder$25 [.model]
        + reorder$5 [.model]
        + ripple [.model]
        + ripple$26 [.model]
        + sm0 [.model]
        + sm1 [.model]
        + sm2 [.model]
[WARNING] In &<id:6355 Instance subckt_242_add_3 add_3>
          Terminal b[0] is connected to POWER/GROUND vdd through the alias
$true
.
[WARNING] In &<id:6355 Instance subckt_242_add_3 add_3>
          Terminal b[1] is connected to POWER/GROUND vdd through the alias
$true
.
[WARNING] In &<id:6355 Instance subckt_242_add_3 add_3>
          Terminal b[2] is connected to POWER/GROUND vdd through the alias
$true
.
[WARNING] In &<id:6355 Instance subckt_242_add_3 add_3>
          Terminal b[3] is connected to POWER/GROUND vdd through the alias
$true
.

... *click*.  this is probably because we hard-code the input of an add
cell (add_3) to "all 1s", because it's being used as an inverter.

somewhere the code is going "hey i will set that input to VDD".

i notice also that zero_NN is ignored (not connected up properly)

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