[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #49 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok another git pull, jean-paul, slowly bashing my way through various
errors:

***** Compare Connections
......................................................
.......................................................

vdd of 'subckt_249_ls_1_subckt_53_sm0_subckt_0_inv_x1' is NOT connected to i1
of
 'subckt_249_ls_1_subckt_4_na2_x1' in netlist 2
through signal subckt_249_ls_1.sm0_mask 1 but to signal vdd

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