[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Feb 21 12:57:28 GMT 2020

On Fri, Feb 21, 2020 at 12:41 PM <bugzilla-daemon at libre-riscv.org> wrote:
> http://bugs.libre-riscv.org/show_bug.cgi?id=178
> --- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> (In reply to Luke Kenneth Casson Leighton from comment #47)
> > btw so that you get some "sync" statements, i've added a new class
> > TestAddMod2 and you'll need to do a "git pull" on both soclayout
> > as well as ieee754fpu.  then:
> >
> > soclayout$ make -f Makefile2 lvx
> sorry:
> ieee754fpu$ git pull
> soclayout$ git pull
> soclayout$ python3 examples/test_part_add.py
> soclayout$ make -f Makefile2 lvx

that's interesting.  sm3 has a component that is zero width (one of
the fun aspects of nmigen is that it doesn't warn when signals are
declared zero-width).

i'll track that down.


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