[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #48 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #47)

> btw so that you get some "sync" statements, i've added a new class
> TestAddMod2 and you'll need to do a "git pull" on both soclayout
> as well as ieee754fpu.  then:
> 
> soclayout$ make -f Makefile2 lvx

sorry:

ieee754fpu$ git pull
soclayout$ git pull
soclayout$ python3 examples/test_part_add.py
soclayout$ make -f Makefile2 lvx

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