[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #47 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #46)
> It truly was the repository of ieee754 that I needed to clone...
> Now, I've a problem with the generated RTLIL:
> 
>   Yosys 0.9 (git sha1 UNKNOWN, clang 3.4.2 -fPIC -Os)
> 
>   1. Executing ILANG frontend.
>   Input filename: part_sig_add.il
>   ERROR: Parser error in line 1: syntax error
>   make: *** [part_sig_add.blif] Error 1
> 
> With the head of the of the il file being:
> 
>   [(sig mask), (sig mask), (sig mask), (sig mask)]
>   partial 12 16 [4, 8] 5
>   partial 8 16 [8, 12] 5

oink??

oh wait - i recognise that: that's debug output from stdout.  you're
running "python3 examples/part_sig_add.py > part_sig_add.il" aren't you?

it should be just "python3 examples/part_sig_add.py".

if you have a look at the source you'll see it creates part_sig_add.il
as part of the "create_ilang()" function.

btw so that you get some "sync" statements, i've added a new class
TestAddMod2 and you'll need to do a "git pull" on both soclayout
as well as ieee754fpu.  then:

soclayout$ make -f Makefile2 lvx

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