[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #35 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hiya jp ok git clone  gitolite3 at libre-riscv.org:soclayout.git

soclayout$ python3 examples/part_sig_add.py
soclayout$ make -f Makefile2

the 2nd Makefile uses nets2.txt which contains $$ substitutions
for $.

i'm currently trying to track down why zero_27...24 have been created
and assigned to carry_in (part_sig_add_cts_r.vst line 1589) and
why zero_24 (and others) is giving Error 38 :width or/and type mismatch

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