[libre-riscv-dev] next tasks
Jean-Paul.Chaput at lip6.fr
Thu Feb 20 13:16:24 GMT 2020
> > The code is available on alliance-check-toolkit in benchs/ao68000 or
> > from https://gitlab.com/Chips4Makers/ao68000/.
It's made for AMS 350nm (4 metal layers / 3 routing), and needs 100%
of free space to complete. I'm using it to improve the router performance
as 100% of free space is too too much.
I will create a 180nm / MOSIS version.
> > In the latter I am working on nMigen intergration.
> ok. you saw yesterday i managed to get that running, with jean-paul's help:
> and it looks like... just did a recent git pull, there's new rules
> %.blif; %.il
> those look great, it means i don't need a special version of
Yes. I created, based on your work a small yosys.py script which takes
the RTLIL generated by nMigen to translate it into blif (maybe I should
merge it with blif2vst.py). Anyway, it avoid mixing the RTLIL to blif
translation with the nMigen file, I think it is more clear cut.
I also added rules to process nMigen designs.
You have a complete exemple under nmigen/alu/ (taken from basic/examples
on nMigen). Configured for the 180nm MOSIS, so with "make gds" you may
be able to have a layout that you can see as GDS with klayout for example
(or magic for instance). Makefile rule "%.il: %.py' only need a python3
binary compatible with nMigen to be present.
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
/v\ Jean-Paul.Chaput at lip6.fr
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