[libre-riscv-dev] next tasks

Michael Nolan mtnolan2640 at gmail.com
Wed Feb 19 15:41:01 GMT 2020

Luke Kenneth Casson Leighton <lkcl at lkcl.net> writes:

> michael would you like to have a go at writing a POWER ISA decoder?

I can give it a go. Need to do some planning on the wiki though, but
just as a rough idea is this going to be more like a modern OOO x86/arm
"decoder" that converts instructions into 1 or more uOps, or more like
the decoder on my custom cpu design which just pulls out the register
fields and selects whether it's an ALU or memory etc. instruction?

Since we're switching between POWER and RISCV at runtime and making an
OOO processor, I'm suspecting it's going to be more like the former.

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