[libre-riscv-dev] electronics tutorial and insights

Staf Verhaegen staf at fibraservi.eu
Tue Feb 18 18:57:34 GMT 2020

Jacob Lifshay schreef op di 18-02-2020 om 05:06 [-0800]:
> Processes are what is got from always @(...) in verilog and process in vhdl
> > 
> > or m.comb += in nmigen. These will be replaced with flipflops and logic. In
> > my terminology the command that replaces statements with is techmap and abc.
> > 
> What you call statements, I would just call combinatorial logic and/or
> data-flow, basically anything that would be expressible using verilog's
> "assign". The idea is to use terms that are less confusing for people who
> are familiar with software but not with HDLs, though I am not necessarily
> doing any better.

Thing is that doing hardware development is different from software as
everything is parallel. So I think that trying to use programmers
terminology for HDL things is more confusing than enlightening.
In HDL the common term used for processing in processes is sequential
logic as opposed to combinatorial logic for non-clocked processing;
other terms is clocked or latched.


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