[libre-riscv-dev] electronics tutorial and insights

Jacob Lifshay programmerjake at gmail.com
Tue Feb 18 13:06:04 GMT 2020

On Tue, Feb 18, 2020, 00:59 Staf Verhaegen <staf at fibraservi.eu> wrote:

> Jacob Lifshay schreef op ma 17-02-2020 om 16:07 [-0800]:
> > On Mon, Feb 17, 2020 at 2:14 PM Luke Kenneth Casson Leighton<
> lkcl at lkcl.net> wrote:
> > > https://libre-riscv.org/3d_gpu/tutorial/
> >
> > Don't forget to use Libre-SOC instead of LibreSOC -- I edited it tofix
> the spelling.
> > Also, the yosys proc command means something a little different
> than"process", it means "translate statement-based code
> segments(confusingly called processes) to gates".
> > http://www.clifford.at/yosys/cmd_proc.html
> Personally I find "statement-based code segments" confusing.

yeah, but the only other descriptions I could think of at the time are
sequential code and procedural code, both of which aren't quite right

Processes are what is got from always @(...) in verilog and process in vhdl
> or m.comb += in nmigen. These will be replaced with flipflops and logic. In
> my terminology the command that replaces statements with is techmap and abc.

What you call statements, I would just call combinatorial logic and/or
data-flow, basically anything that would be expressible using verilog's
"assign". The idea is to use terms that are less confusing for people who
are familiar with software but not with HDLs, though I am not necessarily
doing any better.


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