[libre-riscv-dev] electronics tutorial and insights

Staf Verhaegen staf at fibraservi.eu
Tue Feb 18 08:59:26 GMT 2020

Jacob Lifshay schreef op ma 17-02-2020 om 16:07 [-0800]:
> On Mon, Feb 17, 2020 at 2:14 PM Luke Kenneth Casson Leighton<lkcl at lkcl.net> wrote:
> > https://libre-riscv.org/3d_gpu/tutorial/
> Don't forget to use Libre-SOC instead of LibreSOC -- I edited it tofix the spelling.
> Also, the yosys proc command means something a little different than"process", it means "translate statement-based code segments(confusingly called processes) to gates".
> http://www.clifford.at/yosys/cmd_proc.html

Personally I find "statement-based code segments" confusing.
Processes are what is got from always @(...) in verilog and process in vhdl or m.comb += in nmigen. These will be replaced with flipflops and logic. In my terminology the command that replaces statements with is techmap and abc.

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