[libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or partial) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=72

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|programmerjake at gmail.com    |hacks2019 at platen-software.d
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--- Comment #20 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Tobias: we need to do FP Exception Flags and rounding.  however it's
sufficiently complex, after looking at various implementations, that
i think it's probably best if we use sv2nmigen on Hardfloat-1.zip
http://www.jhauser.us/arithmetic/HardFloat.html

can you take a look at HardFloat_rawFN.v and add support for "parameters"?

i found that i had to modify HardFloat_rawFN.v as follows:
module recFNToRawFN # (par

note the extra space in between recFNtoRawFn and # and (

also i had to remove the "includes" (because i believe they're
pre-processed) and i am not sure about support for "`define".

can you take a look at that and we'll assign a new bugreport under here
plus some budget for it?

this will be a lot more reliable than trying to write an exception/rounder
from scratch.

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