[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
Jean-Paul.Chaput at lip6.fr
Tue Feb 11 18:05:20 GMT 2020
On Tue, 2020-02-11 at 17:04 +0000, bugzilla-daemon at libre-riscv.org wrote:
> --- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
> ok tobias i've created a soclayout repo:
> git clone gitolite3 at libre-riscv.org:soclayout.git
> can i suggest copying the alliance-check-toolkit/benchs/6502/cmos directory, it
> looks dead simple?
No problem. This is all free (GPLed).
> we don't however want to use verilog, we want ilang, so the synthesis-yosys.mk
> file will need changing.
Can you supply me with a ".il" or a deterministic way to produce one
and I will integrate it to alliance-check-toolkit.
My vision of alliance-check-toolkit is to gather all kinds of designs
in it to server as regression tests / benchmarks / examples.
> i just managed to verify that the following (manually-run) yosys
> commands will work:
> set liberty_file
> read_ilang part_sig_add.il
> hierarchy -check -top top
> synth -top top
> dfflibmap -liberty $liberty_file
> abc -liberty $liberty_file
> write_blif test.blif
> and ta-daaa, it produced a blif file!
> if you can modify the mk/synthesis-yosys.mk file that comes with the 6502/cmos
> to take into account we are using ilang, that would make a great start.
Yes, see above.
> we can then pick a simple module as a starting point and go from there.
> later we can do another one with, say, the ARM chip, which has actual
> GPIO pads.
I've also remembered that Coriolis is almost completely configured to
use MOSIS scn6m_deep "real" technology which is a 180nm one.
It can be used to check the whole toolchain down to real layout.
Thanks to Pr. Shimizu who did make the RDS file.
You can then see your design in GDS under Magic.
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