[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

Cole Poirier colepoirier at gmail.com
Tue Feb 11 22:21:38 GMT 2020

Hi Libre-SOC team,

Apologies for not getting back to you about my progress with the Coriolis HDL workflow sooner. I was able to follow the debian 9 installation instructions (https://www.debian.org/releases/stretch/amd64/apds03.html.en <https://www.debian.org/releases/stretch/amd64/apds03.html.en>), however, after completing this and returning to the workflow page (https://libre-riscv.org/HDL_workflow/coriolis2/ <https://libre-riscv.org/HDL_workflow/coriolis2/>) I was confused by the first instruction of "In advance, edit /etc/fstab and add mount points: personally I prefer using mount --bind points” which is followed by a pastable code snippet. I got stuck here and my brain sort of got locked into a loop trying to figure out if this instruction was supposed to be completed on the initial host system and then the user is supposed to follow the debian installation instructions, or… my brain loop just kept collapsing in on itself. I’m sorry my *nix filesystem and boot procedure knowledge is too basic for me to parse this on my own. I’m confused as to what parts of the debian installation guide I should follow, and at what point in the setup procedure I should follow the LSOC instructions.


> On Feb 11, 2020, at 10:05 AM, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
> On Tue, 2020-02-11 at 17:04 +0000, bugzilla-daemon at libre-riscv.org <mailto:bugzilla-daemon at libre-riscv.org> wrote:
>> http://bugs.libre-riscv.org/show_bug.cgi?id=178 <http://bugs.libre-riscv.org/show_bug.cgi?id=178>
>> --- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net <mailto:lkcl at lkcl.net>> ---
>> ok tobias i've created a soclayout repo:
>> git clone  gitolite3 at libre-riscv.org <mailto:gitolite3 at libre-riscv.org>:soclayout.git
>> can i suggest copying the alliance-check-toolkit/benchs/6502/cmos directory, it
>> looks dead simple?
>  No problem. This is all free (GPLed).
>> we don't however want to use verilog, we want ilang, so the synthesis-yosys.mk
>> file will need changing.
>  Can you supply me with a ".il" or a deterministic way to produce one
>  and I will integrate it to alliance-check-toolkit.
>  My vision of alliance-check-toolkit is to gather all kinds of designs
>  in it to server as regression tests / benchmarks / examples.
>> i just managed to verify that the following (manually-run) yosys
>> commands will work:
>> set liberty_file
>> /home/chroot/coriolis/home/lkcl/alliance/install/cells/sxlib/sxlib.lib
>> read_ilang part_sig_add.il
>> hierarchy -check -top top
>> synth -top top
>> dfflibmap -liberty $liberty_file
>> abc -liberty $liberty_file
>> clean
>> write_blif test.blif
>> and ta-daaa, it produced a blif file!
>> if you can modify the mk/synthesis-yosys.mk file that comes with the 6502/cmos
>> to take into account we are using ilang, that would make a great start.
>  Yes, see above.
>> we can then pick a simple module as a starting point and go from there.
>> later we can do another one with, say, the ARM chip, which has actual
>> GPIO pads.
>  I've also remembered that Coriolis is almost completely configured to
>  use MOSIS scn6m_deep "real" technology which is a 180nm one.
>  It can be used to check the whole toolchain down to real layout.
>  Thanks to Pr. Shimizu who did make the RDS file.
>  You can then see your design in GDS under Magic.  
> -- 
>      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
>      /v\     Jean-Paul.Chaput at lip6.fr <mailto:Jean-Paul.Chaput at lip6.fr>
>    /(___)\   work: (33)              
>     ^^ ^^    cell:   home:
>    U P M C   Universite Pierre & Marie Curie
>    L I P 6   Laboratoire d'Informatique de Paris VI
>    S o C     System On Chip
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