[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok tobias i've created a soclayout repo:
git clone  gitolite3 at libre-riscv.org:soclayout.git

can i suggest copying the alliance-check-toolkit/benchs/6502/cmos directory, it
looks dead simple?

we don't however want to use verilog, we want ilang, so the synthesis-yosys.mk
file will need changing.

i just managed to verify that the following (manually-run) yosys
commands will work:

set liberty_file
/home/chroot/coriolis/home/lkcl/alliance/install/cells/sxlib/sxlib.lib
read_ilang part_sig_add.il
hierarchy -check -top top
synth -top top
dfflibmap -liberty $liberty_file
abc -liberty $liberty_file
clean
write_blif test.blif

and ta-daaa, it produced a blif file!

if you can modify the mk/synthesis-yosys.mk file that comes with the 6502/cmos
to take into account we are using ilang, that would make a great start.

we can then pick a simple module as a starting point and go from there.

later we can do another one with, say, the ARM chip, which has actual
GPIO pads.

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