[libre-riscv-dev] Routing a first nmigen disign with Corilis

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Feb 10 16:38:25 GMT 2020

On Mon, Feb 10, 2020 at 4:05 PM Jean-Paul Chaput
<Jean-Paul.Chaput at lip6.fr> wrote:
> Hello Tobias,
> I'm a little surprised that you mention Mauka, Knik & Kite, as they should
> no longer in the doc. They are replaced by Etesian/Coloquinte and Katana.
> Did you use the "devel" branch ? If not, please do so. The "master" is
> terribly late (and the new repository is https://gitlab.lip6.fr/jpc/coriolis.git)

we've got this far:
and it does include "git checkout devel"

tobias did you follow that instruction?

> Alongside with that, and my apologies for the doc to be unclear, you
> will need Alliance and alliance-check-toolkit which are:
> https://gitlab.lip6.fr/jpc/alliance.git
> https://gitlab.lip6.fr/jpc/alliance-check-toolkit.git

i will add these to

> Alliance provide additional CAD tools and some cells libraries.
> Alliance Check Toolkit gives you examples and a complete Makefile
> architecture to automate designs.
> You can extract from the Dockerfile in bootstrap/docker/debian9
> the scripts to install & rebuild in your schroot environement.
> (also take allianceInstaller.sh and socInstaller.py).

> Basically you are correct, as you have Verilog you can directly
> enter Yosys (providing a cell library under the form of ".lib").
> Yosys do not "convert" your design, it synthesize it using the
> standard cells as building block. Then you can place (Etesian)
> then route (Katana). You will get a *symbolic* layout that is
> to be converted in real, but that operation needs to acces the
> technology which is under NDA, so it is delegated to Staf
> Verhaegen.

that bit we will do later: the goal here is to do something - anything
- that allows us to have some reasonably accurate time-estimates for
place-and-route of libresoc modules (any libresoc modules) once
"initial hurdles are completed and documented".

so we just need "something" - not under NDA - to get started.  the
problem is, we don't know what we don't know, so don't know how to
ask, or find what we don't know we need to ask or not ask, if you know
what i mean :)

is there a chip - any chip - any project template, any project example
- which "works", from start to finish (excluding NDA'd tools), using
any geometry (180nm is better), that we can look at, compile
unmodified, so that we can document how to do that?  then, from there,
move on to looking at replacing its verilog code with our own
(actually .il files from yosys more like, but that's another story)?

i'd expect such a chip to be in the alliance-check-toolkit however we
don't even know what we're looking at in order to know which bits we
need, let alone know what to do or how to run them.

we're *literally* completely in the dark, here, having never done this
before - at all - so unless there's a specific tutorial which says, to
make a chip layout do this: "step 1: install these tools.  step 2: get
this project repo.  step 3: cd to this directory.  step 4: run make or
./compile-place-and-route.sh" we're absolutely lost.

thx jean-paul, and apologies for not knowing where to begin, here.


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