[libre-riscv-dev] Routing a first nmigen disign with Corilis

[Jean-Paul Chaput]

On Mon, 2020-02-10 at 16:38 +0000, Luke Kenneth Casson Leighton wrote:
> On Mon, Feb 10, 2020 at 4:05 PM Jean-Paul Chaput
> <Jean-Paul.Chaput at lip6.fr> wrote:
> > 
> > 
> > Hello Tobias,
> > 
> > I'm a little surprised that you mention Mauka, Knik & Kite, as they should
> > no longer in the doc. They are replaced by Etesian/Coloquinte and Katana.
> > 
> > Did you use the "devel" branch ? If not, please do so. The "master" is
> > terribly late (and the new repository is https://gitlab.lip6.fr/jpc/coriolis.git)
> 
> we've got this far:
> https://libre-riscv.org/HDL_workflow/coriolis2/
> and it does include "git checkout devel"
> 
> tobias did you follow that instruction?
> 
> > Alongside with that, and my apologies for the doc to be unclear, you
> > will need Alliance and alliance-check-toolkit which are:
> > 
> > https://gitlab.lip6.fr/jpc/alliance.git
> > https://gitlab.lip6.fr/jpc/alliance-check-toolkit.git
> 
> i will add these to
> https://libre-riscv.org/HDL_workflow/coriolis2/
> 
> > Alliance provide additional CAD tools and some cells libraries.
> > Alliance Check Toolkit gives you examples and a complete Makefile
> > architecture to automate designs.
> > 
> > You can extract from the Dockerfile in bootstrap/docker/debian9
> > the scripts to install & rebuild in your schroot environement.
> > (also take allianceInstaller.sh and socInstaller.py).
> 
> 
> 
> > Basically you are correct, as you have Verilog you can directly
> > enter Yosys (providing a cell library under the form of ".lib").
> > Yosys do not "convert" your design, it synthesize it using the
> > standard cells as building block. Then you can place (Etesian)
> > then route (Katana). You will get a *symbolic* layout that is
> > to be converted in real, but that operation needs to acces the
> > technology which is under NDA, so it is delegated to Staf
> > Verhaegen.
> 
> that bit we will do later: the goal here is to do something - anything
> - that allows us to have some reasonably accurate time-estimates for
> place-and-route of libresoc modules (any libresoc modules) once
> "initial hurdles are completed and documented".
> 
> so we just need "something" - not under NDA - to get started.  the
> problem is, we don't know what we don't know, so don't know how to
> ask, or find what we don't know we need to ask or not ask, if you know
> what i mean :)
> 
> is there a chip - any chip - any project template, any project example
> - which "works", from start to finish (excluding NDA'd tools), using
> any geometry (180nm is better), that we can look at, compile
> unmodified, so that we can document how to do that?  then, from there,
> move on to looking at replacing its verilog code with our own
> (actually .il files from yosys more like, but that's another story)?

  You must create a configuration for alliance-check-toolkit:

    alliance-check-toolkit/etc/mk/users.d/user-LOGIN.mk

    where you define where the various tools are installed
    (look in other ones to have an idea).

  You can try the ARM in alliance-check-toolkit:

    > cd alliance-check-toolkit/benchsARM/cmos/
    > make lvx

    Should take about five minutes. It's symbolic, but should be
    a configuration compatible with 180nm. To actually see the
    results:

    > make cgt

    Then "File -> Open", "arm_chip_cts_r"

    To have a very rough approximation, you can say that one lambda
    equal 180nm.

> i'd expect such a chip to be in the alliance-check-toolkit however we
> don't even know what we're looking at in order to know which bits we
> need, let alone know what to do or how to run them.
> 
> we're *literally* completely in the dark, here, having never done this
> before - at all - so unless there's a specific tutorial which says, to
> make a chip layout do this: "step 1: install these tools.  step 2: get
> this project repo.  step 3: cd to this directory.  step 4: run make or
> ./compile-place-and-route.sh" we're absolutely lost.
> 
> thx jean-paul, and apologies for not knowing where to begin, here.

  No problem. You're welcome.

  The doc is mostly for people who already have a background in ASICs,
  I will try to patch something from my lecture in VLSI to help people
  to orient themselves.

  The up-to-date documentation is supplied directly in the Coriolis
  repository:

     coriolis/documentation/output/index.html

     The links toward the doxygen doc will be invalid a this point,
     but everython else works.

   After installation, it is put in:

     coriolis-2.x/Linux.x86_64/Release.Shared/install/share/doc/coriolis2/en/html/index.html

_______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
-- 

      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33) 01.44.27.53.99              
     ^^ ^^    cell:      06.66.25.35.55   home: 09.65.29.83.38

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip