[libre-riscv-dev] Routing a first nmigen disign with Corilis
Jean-Paul.Chaput at lip6.fr
Mon Feb 10 16:10:19 GMT 2020
I'm a little surprised that you mention Mauka, Knik & Kite, as they should
no longer in the doc. They are replaced by Etesian/Coloquinte and Katana.
Did you use the "devel" branch ? If not, please do so. The "master" is
terribly late (and the new repository is https://gitlab.lip6.fr/jpc/coriolis.git)
Alongside with that, and my apologies for the doc to be unclear, you
will need Alliance and alliance-check-toolkit which are:
Alliance provide additional CAD tools and some cells libraries.
Alliance Check Toolkit gives you examples and a complete Makefile
architecture to automate designs.
You can extract from the Dockerfile in bootstrap/docker/debian9
the scripts to install & rebuild in your schroot environement.
(also take allianceInstaller.sh and socInstaller.py).
Basically you are correct, as you have Verilog you can directly
enter Yosys (providing a cell library under the form of ".lib").
Yosys do not "convert" your design, it synthesize it using the
standard cells as building block. Then you can place (Etesian)
then route (Katana). You will get a *symbolic* layout that is
to be converted in real, but that operation needs to acces the
technology which is under NDA, so it is delegated to Staf
On Sat, 2020-02-08 at 18:44 +0100, Tobias Platen wrote:
> I have read the documentaion of corilis2, and now I want to route a first simple
> Yosys and the blif format have been mentioned, so I guess exporting verilog from
> then running yosys to convert the verilog to blif. Then read the netlist into corilis2,
> map to cells from the target technology. Then place and route can be done with Mauka,
> Knik and Kite.
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