[libre-riscv-dev] memory interface diagram woes

whygee at f-cpu.org whygee at f-cpu.org
Tue Apr 28 14:33:23 BST 2020

On 2020-04-28 13:56, Luke Kenneth Casson Leighton wrote:
> fail.  on to version *12*.  it's about 90 minutes to draw and verify
> each diagram.

have a look at http://www.falstad.com/circuit/circuitjs.html
it has some digital simulation capabilities, and lets you
exchange the designs with simple minified links.
Then you can integrate digital (sub-)circuits as IFRAMEs
in webpages to explain and expose the principles of your design.
It's not the very best system but it's incredibly useful
and flexible. You won't use DIA anymore ;-)

> l.

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