[libre-riscv-dev] memory interface diagram woes
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Apr 28 15:26:29 BST 2020
On Tue, Apr 28, 2020 at 2:33 PM <whygee at f-cpu.org> wrote:
> On 2020-04-28 13:56, Luke Kenneth Casson Leighton wrote:
> > fail. on to version *12*. it's about 90 minutes to draw and verify
> > each diagram.
> have a look at http://www.falstad.com/circuit/circuitjs.html
> it has some digital simulation capabilities, and lets you
> exchange the designs with simple minified links.
oooo i looove it.
another one, circuitdiagram
> Then you can integrate digital (sub-)circuits as IFRAMEs
> in webpages to explain and expose the principles of your design.
> It's not the very best system but it's incredibly useful
> and flexible. You won't use DIA anymore ;-)
that's a great idea.
More information about the libre-riscv-dev