[libre-riscv-dev] memory interface diagram woes

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Apr 28 12:56:12 BST 2020

fail.  on to version *12*.  it's about 90 minutes to draw and verify
each diagram.

this one, version 11: the "LD" latch correctly implements the LD-ST
Port API and captures the outputted data from the Port, however the
Port API only sets the "LD_OK" signal for one cycle, where the REQ_WR
signal needs to be sustained.  so a *separate* latch is needed for
capturing the data, and a *separate* latch for requesting and
acknowledging the LD WRITE-to-register (REQ_WR1 + GO_WR1)

whilst it might be said that this is "better" implemented as a nmigen
FSM, it's actually not, because of the multiple levels of interaction.
one FSM would be inadequate, because it's actually *three*
state-progressing FSMs in one, the behaviour of each actually changing
depending on whether the operation is LD, LD-with-UPDATE, or ST.

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