[libre-riscv-dev] memory interface diagram woes

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Apr 27 13:38:26 BST 2020

scream! 2 days writing out the 10th version of the logic-diagram for
LD/ST in 12 months, only to note that POWER has a 2-in 2-out variant
of LD called "update" which optionally puts the computed Effective
Address out on RA as a 2nd write source!

fortunately i can i believe cookie-cut an existing diagram
this contains multi-write protection already however the difference is
that it needs to switch between single-write and dual-write. i think i
can do that by "fake" setting one of the SR Latches to "already

patience, patience...


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