[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Apr 3 20:21:57 BST 2020


--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #9)
> (In reply to Luke Kenneth Casson Leighton from comment #5)
> > (In reply to whitequark from comment #4)
> > > Ah, there's another option that you might find interesting. Yosys has a
> > > `$sr` coarse cell. 
> > 
> > yes.  this i _believe_ is what Staf has implemented for us, in the nsxlib
> > Cell Library:
> > http://bugs.libre-riscv.org/show_bug.cgi?id=154#c21
> Not really, I implemented the standard cells implementing the SR latches. A
> variant with NOR gates and one with NAND gates and two drive strengths of
> each.

i think that's what i meant.

ok so these are called nsnrlatch and srlatch, and there are times-1 and times-4

> Yosys and synthesis the logic netlist coming from nMigen needs to mapped to
> the cells in the library is on a higher level than what I am doing.

my main reason to cross-ref what you kindly wrote for our use was to highlight
that it had happened.

so let me try to understand:

* yosys $sr (and variants) will need to map to these cells (nsnrlatch_xN
  and srlatch_xN).

  will this need patches (or a plugin) into yosys?

* nmigen will need to map to $sr

  i presume that given that yosys already has $sr, only nmigen will need
  augmenting to produce $sr?

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