[libre-riscv-dev] [Bug 276] SR NAND Latch needed in nmigen

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Fri Apr 3 19:51:45 BST 2020


Staf Verhaegen <staf at fibraservi.eu> changed:

           What    |Removed                     |Added
                 CC|                            |staf at fibraservi.eu

--- Comment #9 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> (In reply to whitequark from comment #4)
> > Ah, there's another option that you might find interesting. Yosys has a
> > `$sr` coarse cell. 
> yes.  this i _believe_ is what Staf has implemented for us, in the nsxlib
> Cell Library:
> http://bugs.libre-riscv.org/show_bug.cgi?id=154#c21

Not really, I implemented the standard cells implementing the SR latches. A
variant with NOR gates and one with NAND gates and two drive strengths of each.

Yosys and synthesis the logic netlist coming from nMigen needs to mapped to the
cells in the library is on a higher level than what I am doing.

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