[libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Apr 1 20:06:54 BST 2020


Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
                 CC|                            |programmerjake at gmail.com

--- Comment #14 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Michael Nolan from comment #13)
> I've got something in decoder/selectable_int.py. It uses Power's bit
> ordering so it should be good for the compiler but something to be aware of
> if it's used anywhere else.
> I'm not sure what to do about left shift and right shift. Should
> SelectableInt (0x10, bits=8) << 4 equal SelectableInt(0x100, bits=12) or
> SelectableInt(0x00, bits=8)

I would assume shift left is still shift left. You can check which pseudo-code
gets run by the slw instruction since it's what gcc produces for the <<

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