[libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Apr 1 22:55:06 BST 2020


--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #13)
> I've got something in decoder/selectable_int.py. It uses Power's bit
> ordering so it should be good for the compiler but something to be aware of
> if it's used anywhere else.

ahh superb.  ok.

> It's also unsigned only, I'm not sure how much that matters right now

as jacob pointed out, we can find out soon enough.

i do feel that we maay need to put carry-in and carry-out into the
Int class (somehow).  also, perhaps rewrite the pseudo-code fragments
to match those, then propose them back to the OpenPOWER Foundation.

just a thought.

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