[libre-riscv-dev] power pc

[Hendrik Boom]

On Fri, Oct 25, 2019 at 06:03:22AM +0800, Luke Kenneth Casson Leighton wrote:
> On Thursday, October 24, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> 
> > https://libre-riscv.org/openpower/
> 
> 
> Wrote up an idea on how to fit Compressed. There are only 11 bits available
> for 16 bit ops which is really tight.
> 
> Therefore the idea is to have up to 8 "pages" where each "page" may be
> activated for up to 14 instructions, or permamently if 0b1111 is specified.
> 
> OP0 and OP1 each have their own page specifiers and their own CSR bits.
> 
> If the (measly) 11 bits were divided into 3 bits for opcode (then 2x 3 bits
> for registers or whatever, all TBD), that's 8 compressed instructions per
> page per opcode.
> 
> 8 x 3 x 2 gives a total of 48 Compressed 11 bit operations.
> 
> Which is still tiny but better than nothing.
> 
> The advantage of dual paging is that the most commonly used ones can be
> activated and left on for any given function.

Can the page specifiers nest?  So that if you have the page of commonly 
used ones active you could use one of the uncommon ones for an 
instruction and then be back to the commonly used ones?

A limit on page specifier nesting is probably good.

How do page specifiers interact with subroutine calls and jumps?

-- hendrik