[libre-riscv-dev] power pc

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Oct 24 23:03:22 BST 2019

On Thursday, October 24, 2019, Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> https://libre-riscv.org/openpower/

Wrote up an idea on how to fit Compressed. There are only 11 bits available
for 16 bit ops which is really tight.

Therefore the idea is to have up to 8 "pages" where each "page" may be
activated for up to 14 instructions, or permamently if 0b1111 is specified.

OP0 and OP1 each have their own page specifiers and their own CSR bits.

If the (measly) 11 bits were divided into 3 bits for opcode (then 2x 3 bits
for registers or whatever, all TBD), that's 8 compressed instructions per
page per opcode.

8 x 3 x 2 gives a total of 48 Compressed 11 bit operations.

Which is still tiny but better than nothing.

The advantage of dual paging is that the most commonly used ones can be
activated and left on for any given function.

Perhaps OP0 is for INT Compressed ops, and OP1 for FP?

FMAC is top priority. Even using overwriting of dest as one of the srces
(rd += rs1 * rs2) that is still bits for registers, and that's without rd
-= rs1 * rs2.

Nice thing here is, we get to design the Compressed instruction set to be

Thoughts, alternatives?


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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