[libre-riscv-dev] M-class SoC Emulator

[Luke Kenneth Casson Leighton]

On Fri, Nov 22, 2019 at 4:28 PM an0oo0nym0oo0us OoO <
oooanoonymoous at gmail.com> wrote:

> Hello,
>
> I would like to write drivers for HelenOS for M-class Soc. Have you had any
> emulator for this SoC yet?
>

hiya anoooonymouse, (cc'ing you as you replied to a mailing list which
requires subscription)

the core is Simple-V, a vectorisation standard.
https://libre-riscv.org/simple_v_extension/specification/

part of the development of the standard clearly needed a simulator, plus
unit tests, to check if it would be as "compact" and efficient as
expected.  that's here:
https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=tree;h=refs/heads/sv;hb=refs/heads/sv

and the unit tests here:
https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=tree;h=refs/heads/sv;hb=refs/heads/sv

answer: yes, however it's an early version that (very usefully) showed some
inefficiencies [not compact enough].  we therefore began work on SVP and
VBLOCK:

https://libre-riscv.org/simple_v_extension/sv_prefix_proposal/
https://libre-riscv.org/simple_v_extension/vblock_format/

since then, we realised that the RISC-V Foundation do not deserve our time
and efforts to improve the RISC-V ISA, particularly as they are actively
hostile to Libre Projects (this despite being a Trademark).
http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-October/003035.html

i opened up discussions with the OpenPower Foundation Director, Hugh
Blemings, and was surprised and delighted to find that they have been
thinking exactly along the lines of how to include Libre Projects in the
OpenPower Foundation as peer members.

the Vectorisation principles of SimpleV may be applied to PowerISA just as
well as they can to RISC-V (or in fact any ISA).

we've not got any further than that, as i am presently organising a
crowdfunding campaign which will raise funds and create a customer for the
planned processor in the future.

l.