[libre-riscv-dev] sv2nmigen, switch to power isa
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Nov 4 21:02:02 GMT 2019
On Tuesday, November 5, 2019, Tobias Platen <hacks2019 at platen-software.de>
> I've recently added working preprocessor to the parser, so that broken
> system verilog code appears as docstrings in the python output. Next I
> plan to convert the load store unit. However if the power ISA is
> implemented this will lead to a different type of MMU. For example the
> power9 has a radix MMU.
I know. Fricking nuisance.
Can you hold off doing conversion work while we wait to hear from Hugh
Also put in that bugreport, you saw what Jacob did for #145.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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