[libre-riscv-dev] sv2nmigen, switch to power isa

Tobias Platen hacks2019 at platen-software.de
Mon Nov 4 20:51:04 GMT 2019

I've recently added working preprocessor to the parser, so that broken 
system verilog code appears as docstrings in the python output. Next I
plan to convert the load store unit. However if the power ISA is 
implemented this will lead to a different type of MMU. For example the 
power9 has a radix MMU.


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