[libre-riscv-dev] sv2nmigen, switch to power isa
hacks2019 at platen-software.de
Tue Nov 5 18:47:49 GMT 2019
On 04.11.19 22:02, Luke Kenneth Casson Leighton wrote:
> On Tuesday, November 5, 2019, Tobias Platen <hacks2019 at platen-software.de>
>> I've recently added working preprocessor to the parser, so that broken
>> system verilog code appears as docstrings in the python output. Next I
>> plan to convert the load store unit. However if the power ISA is
>> implemented this will lead to a different type of MMU. For example the
>> power9 has a radix MMU.
> I know. Fricking nuisance.
> Can you hold off doing conversion work while we wait to hear from Hugh
I have not done any converasation work in the last day, and I plan no
> Also put in that bugreport, you saw what Jacob did for #145.
I was not aware of http://bugs.libre-riscv.org/show_bug.cgi?id=145
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