[libre-riscv-dev] multi issue

[Luke Kenneth Casson Leighton]

Oh, nearly forgot, there is a potential reason for having separate
instruction decode Q from instruction issue Q, the SV vectorisation
hardware "for-loop" which issues multiple element based sub-instructions
based on the VL vector length.

This engine will live *between* these two queues.

So the instruction issue Q will be much larger and take a lot more entries
than the instruction decode Q.

The opportunity therefore exists to "normalise" the instruction to a
uniform length, with partial decode.

Also, predication gets added at the issue Q (creates a shadow, there will
need to be special predication Function Units, very similar to Branch
Units).

There will also need to be a special unit for that vectorised MV.X
instruction we discussed, Jacob.

L.



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