[libre-riscv-dev] multi issue
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu May 30 23:09:58 BST 2019
Ok so I have a partially tested instruction queue that I plan to drop
uniform instructions into, the actual one used for RISCV will need length
The queue can take *multiple* entries in and out per clock which is crucial
to have for multi issue
When turned into a RISCV queue the input side will be a fixed width and
fixed fraction of a cache line.
Maybe, to not waste too much power in terms of routing, it would help to be
able to specify that the Q have an additional offset argument, saying where
the start is to be copied from.
Then it would be possible to throw say a quarter or a half of a cache line
at the Q, and tell it to ignore the first N halfwords.
Without that trick, the routing *outside* the Q becomes an N to M way
With it, the routing is just an N to 1 multiplexer.
This is an extraordinary amount of detail needed for something that you
would think, in software alone, would be so simple and straightforward!
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