[libre-riscv-dev] Progress on KCP53000B and its IFU

[Samuel Falvo II]

I think I've completed the (Tilelink) IFU design.  I emphasize
"think", because without the rest of the processor being built, it's
not yet possible to know if I'm truly done or not.

My next major step is to work on the IXU design.  But, before that
works, I would like to make an intermediate design which couples the
IFU with the ROMA core (thus letting me read from flash ROM) and
passing the lower 8-bits of each "instruction" fetched out to a set of
LEDs.  This will provide visual confirmation that everything is
working.

Per previous discussions, I could take the time to also create a
Wishbone B4 pipelined IFU as well.  Unlike Luke, I have no particular
deadlines for the Kestrel project, so I'll let Luke decide the
priority here.

*  *  *

Unrelated, I now have another group interested in the evolution of the
Kestrel Computer Project.  In particular, I collaborate on the design
and construction of various fursuit/cosplay ideas, and my Kestrel
project has come to light there.  We have been having some issues with
the Teensie board we've been using in the past (not enough I/Os), and
with Raspberry Pis (too *slow* I/O; the AXI -> AHB/APB bridge is just
too costly to keep up sometimes), and so now they're interested in the
possibility of using FPGAs programmed with a KCP53000 or KCP53000B
processor for their embedded development needs.

-- 
Samuel A. Falvo II