[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #27 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
Ok found a 6 bit ripple carry adder,
It produces a 4 bit answer, however only
the top 2 bits and sign matter.
According to the Tanako paper DS needs
a number that is signed and is between3
thresholds
-0.25
0
0.5

something like that.

This would be in 2 bits plus the sign.

This gives the 1 bit qj+1 which must be either -1 0 or +1

The algorithm can be checked against sqrt 
because apparently the OTFC stage produces
both Isqrt and Sqrt.

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