[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #26)
> (In reply to Luke Kenneth Casson Leighton from comment #25)
> > Created attachment 15 [details]
> > 6 bit ripple add
> > 
> > 6 bit ripple adder
> 
> the attachment is just a 3-bit + 3-bit -> 4-bit adder.
> a = Signal(3)
> b = Signal(3)
> y = Cat(a, C(0, 1)) + Cat(b, C(0, 1))

Ah ok.

https://www.researchgate.net/publication/234151562_An_FPGA_Based_Generic_Framework_for_High_Speed_Sum_of_Absolute_Difference_Implementation/download

Apparently Tanako may mean just 2 Full Adders chained together.

6 bits in, 3 bits out. Might need 2 Full Adders and 1 Half.

Arg! :) Just the worst when academics assume entire areas of knowledge by
readers.

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