[libre-riscv-dev] [Bug 44] IEEE754 FPU inverse-sqrt

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=44

--- Comment #26 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #25)
> Created attachment 15 [details]
> 6 bit ripple add
> 
> 6 bit ripple adder

the attachment is just a 3-bit + 3-bit -> 4-bit adder.
a = Signal(3)
b = Signal(3)
y = Cat(a, C(0, 1)) + Cat(b, C(0, 1))

-- 
You are receiving this mail because:
You are on the CC list for the bug.