[libre-riscv-dev] chinese sponsor, looking to design an ECP5-based dev board

[Luke Kenneth Casson Leighton]

On Tue, May 7, 2019 at 12:43 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Mon, May 6, 2019 at 4:06 PM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >  that's the entire power budget of the entire design blown solely and
> > exclusively on the DRAM.
> I was expecting the power budget of 2.5W to be just for the SoC, not
> the RAM as well.

 one of the clients / customers, i can't say what their application
is: they'll definitely need to pay the USD $2m for an ASIC-integrated
LPDDR3/LPDDR4 interface - the application is so small that yes, 2.5W
is pushing it for the entire design.

 for these purposes however, 2.5 W for the processor and under 0.5W
for the DRAM is well within the thermal limits of a credit-card-sized
PCB, no heat sinks required.

> I wouldn't expect the FPGA-based solution to be that
> low power anyway, since FPGAs are less efficient than ASICs. I'd
> expect it to be less than 10W for the FPGAs and a watt or so for the
> memory.

 section 3.10 of the ECP5 data sheet, the core power supply current
for the LFE5UM5G-85F is 212mA (1.2v), so around the 250mW mark.  the
SERDES channels typically are around.... estimated... 60mW...

 so it's really not that bad.  from working with EOMA68 i know that a
bank of 4 8x DDR3 ICs @ a 400mhz clock requires 350mW.

 so... even with 2x ECP5 FPGAs, if sticking to just a 32-bit bank
width, under 3.5 watts is still achievable, which is the kind of range
where heat sinks aren't needed, and costs can be kept down.


> >  by sticking to the lower speeds, we avoid the data corruption by
> > simply not pushing the ICs beyond the point where a Chinese ODM cannot
> > do the layout and the task has to be allocated to a Taiwan or Western
> > subcontractor, who will charge a minimum of USD $50k.
> Note that there are plenty of capable Chinese contractors that can do
> high-frequency PCB design (not that they will be cheaper).

 finding reputable ones has taken me... literally years.  remember,
jacob, i've been doing component sourcing, PCB and 3D design for 7
years now.



> If the memory bus has a few extra data lines, that's close to all that
> needs to be added to the PCB to support ECC (assuming the memory
> itself does anyway). I wasn't expecting the final SoC to require ECC,
> but if we designed it so we could convert a few extra GPIO pins to
> additional bits for the memory bus, it should have a quite low
> incremental cost.

 i'll see if they're happy to do twin LPDDR3 ICs (or use the MCM ICs
from samsung that have 2x 32-bit-wide LPDDR3 dies plus an eMMC die on
the same chip).

 ohhh rats, i nearly forgot about eMMC.

 must have that conversation with florent from enjoy-digital.

l.